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MC9S08L*2CLH MKL27Z64VLH4 托盘

￥6.3元/件中国广东深圳

产品属性

MKL27Z64VLH4 托盘:: MKL27Z64VLH4 托盘

品牌:: NXP

封装形式:: DIP

类型:: 数字集成电路

用途:: 军工

功能:: 单片机

导电类型:: 双极型

封装外形:: 金属壳圆形型

集成度:: 小规模(<50)

型号:: MC9S08LG32CLH

批号:: 2017+

8.13.1 Features

• Maximum data rates of 30 Mbit/s in master mode and 25 Mbit/s in sl*e mode for SPI

function*onnected to all digital pins except PIO0_10 and PIO0_11.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.

• Master and sl*e operation.

• Data can be tran*itted to a sl*e without the need to re*coming data. Thi*an

be useful while setting up an SPI memory.

• Co*ol information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• One Sl*e Select input/output with selectable polarity and flexible usage.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

8.14 I2C-bus interface

The I2C-bus is bidirectional for inter-IC co*ol using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a tran*itter with the

capability to both receive and send informati*uch a*emory). Tran*itters and/or

receiver*an operate in either master or sl*e mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

co*olled by more than one bu*aster connected to it.

The I2C-bus functi* are movable functi* and can be assigned through the switch

matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the

electrical characteristics to support the full I2C-bus specificati*ee Ref. 1).

8.14.1 Features

• Supports standard and fast mode with data rates of up to 400 kbit/s.

• Independent Master, Sl*e, and Monitor functi*.

• Supports both Multi-master and Multi-master with Sl*e functi*.

• Multiple I2C sl*e addresses supported in ha*are.

• One sl*e addres*an be selectively qualified with a bit mask or an address range in

order to respond to multiple I2C bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Supported by on-chip ROM API.

• If the I2C functi* are connected to the true open-drain pins (PIO0_10 and

PIO0_11), the I2C supports the full I2C-bus specification:

– Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA

and SCL pin*onnected to the I2C-bus are floating and do no*sturb the bus.

– Supports Fast-mode Plus with bit rates up to 1 Mbit/s

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